1. Field of the Invention
The present invention relates to the field of semiconductor packaging, and, more particularly, to thermal management of stacked-chip packages.
2. Description of Related Art
In stacked-chip packaging, multiple integrated circuit chips can be packaged in a single package structure in a vertically stacked manner. This increases stack density, making the package structure smaller, and often reduces the length of the path that signals must traverse between chips. Thus, stacked-chip packaging tends to increase the speed of signal transmission between or among chips. Additionally, stacked-chip packaging allows chips having different functions to be integrated in a single package structure. Use of through silicon vias (TSV) has been a key technology in realizing stacked-chip packaging integration due to the ability to provide short vertical conductive paths between chips.
However, thermal management of 3-D designs has been challenging. To maintain normal operation of the chip, the chip must be maintained within a limited operation temperature range. Operating temperatures in excess of the limited operation temperature range results in chip performance drop, reduced reliability or damage. Existing stacked-chip packages usually include a heat sink, which is bonded to a lower chip using adhesives and that covers the upper chips of the package.
In current chip processing the surface of the chip is covered with a protective layer, which has a low thermal conductivity and therefore hinders conducting of the heat from the chip interior, where it is produced, to the surrounding environment. Even if the heat sink is disposed on the lower chip of the stacked-chip package structure, the protective layer likewise hinders thermal conductance between the lower chip and the heat sink, thus affecting operation and reliability of the stacked-chip package structure.